In the design of integrated circuits, it is known that designers typically utilize one or more libraries of functional circuit elements, commonly known as “cells,” to design circuits as part of one or more such integrated circuits. These cells are typically standardized in that they have known electrical characteristics such as, for example, propagation delay, capacitance and inductance. Nonetheless, designers implement some form of timing analysis to attempt to ensure that timing constraints are met as one of the requirements before the integrated circuit is submitted for tape out in the manufacturing process. Two such well-known timing analyses are Static Timing Analysis (STA) and Circuit Level Analysis (CLA). The two approaches are typically both performed and then an attempt is made to correlate the results. However, when performing STA, there are multiple sources of error when correlated to CLA timing results that are frequently encountered. A first source of error is due to the mismatch of the technology-dependent characterization parameters used and the electrical parameters encountered in the actual circuit when STA is performed. A second source of error is due to the STA tool itself not being able to achieve accurate delay calculation results even when the characterization parameters used during the timing model characterization process are appropriate.